PPC600 Family Debugger | 21
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The following access class attributes are available:
If an Access class attributes is specified without an access class, TRACE32 PowerView will automatically
add the default access class of the used command. For example, Data.List U:0x100 will be changed to
Data.List UP:0x100.
Access Classes to Other Addressable Core and Peripheral Resources
The following access classes are used to access registers which are not mapped into the processor’s
memory address space.
SPRs and PMRs are addressed by specifying the register number after the access class.
Cache
Memory Coherency
The following table describes which memory will be updated depending on the selected access class
Access Class Attributes Description
E Use real-time memory access
A Given address is physical (bypass MMU)
U TS (translation space) == 1 (user memory)
S TS (translation space) == 0 (supervisor memory)
Access Class Description
SPR Special Purpose Register (SPR) access
PMR Performance Monitor Register (PMR) access
Access Class D-Cache I-Cache L2 Cache Memory (uncached)
DC: updated not updated not updated not updated
IC: not updated updated not updated not updated
L2: not updated not updated updated not updated
NC: not updated not updated not updated updated
D: updated not updated updated updated
P: not updated updated (*) updated updated
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