Need help?Do you have a question about the Lauterbach TRACE32 and is the answer not in the manual?
General| Operating System Support (Host) | Windows, Linux |
|---|---|
| Manufacturer | Lauterbach GmbH |
| Category | Debug and Trace Tool |
| Supported Architectures | ARM, Power Architecture, RISC-V, x86 |
| Interface | JTAG, SWD, Nexus, Aurora |
| Features | Debugging, tracing, multicore debugging |
| Host Interface | USB, Ethernet |
| IDE Integration | Eclipse |
| Scripting Language | Practice |
| Power Measurement | Yes (requires specific PowerProbe hardware) |
| Trace Technology | Instruction Trace, Data Trace |
| License Type | Floating license, node-locked license available |
| Software Compatibility | Supports various compilers and toolchains |
Set BDM clock frequency.
Display target configuration.
Configure debugger according to target topology.
Control pin 8 of debug connector.
Configure driver strength of TCK pin.
Control QACK pin.
Select the target processor.
Lock and tristate the debug port.
Enable non-intrusive run-time memory access.
Select target operation mode.
Enable debugging of critical interrupts.
Enable on-the-fly breakpoint setup.
Prevent data cache line load/flush in debug mode.
Display MMU translation table page by page.
Display MMU translation table compactly.
Load MMU table from CPU.
Set an MMU TLB entry.
Freeze counters while core halted.
Freeze counter in certain core states.
Command has no function.
Adjust range breakpoint in on-chip resource.
Disable NEXUS trace register control.
Enable NEXUS trace register control.
Reset on-chip trigger settings.
Enable special on-chip breakpoints.
Adjust HLL breakpoint in on-chip resource.
View on-chip trigger setup window.
Select interface for tracing.
Details of the JTAG Connector MPC85XX (COP).
Guides to other related TRACE32 documents.
Debugger drives output pins at VCCS pin level.
Recommendations for connecting/disconnecting debug cable.
Placement and signal recommendations for JTAG/BDM connectors.
Lists reasons and fixes for SYStem.Up command errors.
Checks for target power and debug cable connection issues.
Issues with processor identification or JTAG communication.
Troubleshooting unexpected target reset behavior.
Diagram of basic BDM interface configuration.
Overview of software and on-chip breakpoints.
Categories for memory access and resources.
Discussion of memory coherency and cache types.
Explains MESI protocol states and flags.
How to view cache contents using CACHE.DUMP.
Configuration for SMP debugging.
Display contents of TLB0.
Display contents of TLB1.
Load TLB0 from CPU to debugger-internal table.
Load TLB1 from CPU to debugger-internal table.
To Next Page
