EasyManuals Logo

Lauterbach TRACE32 User Manual

Lauterbach TRACE32
56 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #30 background imageLoading...
Page #30 background image
PQIII Debugger | 30
©
1989-2021 Lauterbach GmbH
SYStem.CPU Select the target processor
Select the target processor or target core. If the target processor is not available in the CPU selection of the
SYStem window, or if the command results in an error,
check if the licence of the debug cable includes the desired processor. You will find the
information in the VERSION window.
check if the debugger software is sufficiently recent to support the target processor. The
debugger software version can be looked up in the VERSION window. If the processor release
occurred after the debugger software release, the processor is most likely not supported. Please
check the Lauterbach download center (www.lauterbach.com) for updates. If the debugger
software version from the download center also does not support the processor, please contact
technical support and request a software update.
If you are unsure about the processor, try SYStem.DETECT CPU for automatic detection.
SYStem.LOCK Lock and tristate the debug port
Default: OFF.
If the system is locked, no access to the debug port will be performed by the debugger. While locked, the
debug connector of the debugger is tristated. The main intention of the SYStem.LOCK command is to give
debug access to another tool. The command has no effect for the simulator.
Format: SYStem.CPU <cpu_name>
<cpu_name>: MPC85XX | MPC8540 | MPC8560
Format: SYStem.LOCK [ON | OFF]

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Lauterbach TRACE32 and is the answer not in the manual?

Lauterbach TRACE32 Specifications

General IconGeneral
Operating System Support (Host)Windows, Linux
ManufacturerLauterbach GmbH
CategoryDebug and Trace Tool
Supported ArchitecturesARM, Power Architecture, RISC-V, x86
InterfaceJTAG, SWD, Nexus, Aurora
FeaturesDebugging, tracing, multicore debugging
Host InterfaceUSB, Ethernet
IDE IntegrationEclipse
Scripting LanguagePractice
Power MeasurementYes (requires specific PowerProbe hardware)
Trace TechnologyInstruction Trace, Data Trace
License TypeFloating license, node-locked license available
Software CompatibilitySupports various compilers and toolchains

Related product manuals