PQIII Debugger | 47
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1989-2021 Lauterbach GmbH
CPU specific tables in MMU.SCAN <table>
MMU.Set Set an MMU TLB entry
Sets the specified MMU TLB table entry in the CPU. The parameter <tlb> is not available for CPUs with only
one TLB table.
TLB0 Loads the TLB0 from the CPU to the debugger-internal translation table.
TLB1 Loads the TLB1 from the CPU to the debugger-internal translation table.
Formats: MMU.Set TLB0 <index> <mas1> <mas2> <mas3> <mas7>
MMU.Set TLB1 <index> <mas1> <mas2> <mas3> <mas7>
MMU.<table>.SET (deprecated)
<index>: TLB entry index. From 0 to (number of TLB entries)-1 of the specified TLB table
<mas1>:
<mas2>:
<mas3>:
<mas7>:
Values corresponding to the values that would be written to the MAS registers
in order to set a TLB entry. See the processor’s reference manual for details on
MAS registers.
MAS7 contains the most significant bits of the physical 36 bit address (e500v2
cores only).
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