PQIII Debugger | 48
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CPU specific BenchMarkCounter Commands
The BenchMarkCounter features are based on the core’s performance monitor, accessed through the
performance monitor registers (PMR). PMC access is only possible while the core is halted.
Notes:
• BMC.PROfile and BMC.SnoopSet are not supported.
• For information about architecture-independent BMC commands, refer to “BMC”
(general_ref_b.pdf).
• For information about architecture-specific BMC commands, see command descriptions below.
• Events can be assigned to BMC.<counter>.EVENT <event>. For descriptions of available events,
please check Freescale’s core reference manual.
BMC.FREEZE Freeze counters while core halted
Enable this setting to prevent that actions of the debugger have influence on the performance counter. As
this feature software controlled (no on-chip feature), some events (especially clock cycle measurements)
may be counted inaccurate even if this setting is set ON.
BMC.<counter>.FREEZE Freeze counter in certain core states
Halts the selected performance counter if one or more of the enabled states (i.e. states set to ON) match the
current state of the core. If contradicting states are enabled (e.g. SUPERVISOR and USER), the counter will
be permanently frozen. The table below explains the meaning of the individual states.
Format: BMC.FREEZE [ON | OFF]
Format: BMC.<counter>.FREEZE <state> [ON | OFF]
<state>: USER | SUPERVISOR | MASKSET | MASKCLEAR
<state> Dependency in core
USER Counter frozen if MSR[PR]==1
SUPERVISOR Counter frozen if MSR[PR]==0
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