PQIII Debugger | 40
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SYStem.Option.RESetBehavior Set behavior when target reset detected
Defines the debugger’s action when a reset is detected. Default setting is Disabled. The reset can only be
detected and actions taken if it is visible to the debugger’s reset pin.
SYStem.Option.SLOWRESET Relaxed reset timing
This system option defines, how the debugger will test JTAG_RESET. For some system mode changes, the
debugger will assert JTAG_RESET. By default (OFF), the debugger will release RESET and then read the
RESET signal until the RESET pin is released. Reset circuits of some target boards prevent that the current
level of RESET can be determined via JTAG_RESET. If this system option is enabled, the debugger will not
read JTAG_RESET, but instead waits up to 4 s and then assumes that the boards RESET is released.
SYStem.Option.STEPSOFT Use alternative method for ASM single step
This method uses software breakpoints to perform an assembler single step instead of the processor’s built-
in single step feature. Works only for software in RAM. Do not turn ON, unless advised by Lauterbach.
Format: SYStem.Option.RESetBehavior <mode>
<mode>: Disabled
AsyncHalt
Disabled No actions to the processor take place when a reset is detected.
Information about the reset will be printed to the message AREA.
AsyncHalt Halt core as soon as possible after reset was detected. The core will halt
shortly after the reset event.
Format: SYStem.Option.SLOWRESET [ON | OFF]
Format: SYStem.Option.STEPSOFT [ON | OFF]
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