PQIII Debugger | 33
©
1989-2021 Lauterbach GmbH
CPU specific SYStem.Option Commands
SYStem.Option.CINTDebug Enable debugging of critical interrupts
If the CPU enters a critical interrupt, MSR_DE will be cleared, which means that breakpoints are disabled.
Enable this option in order to set a breakpoint in a critical interrupt handler. When enabled, the debugger will
stop the CPU upon entering a critical interrupt, set MSR_DE and run the CPU again.
Please note that this option will have influence on the run-time behavior (i.e. performance loss) of the
system, as the debugger needs to stop the CPU to set MSR_DE. As alternative to this option, patch the
application to re-enable MSR_DE in the critical interrupt handlers. After MSR_DE has been restored, it is
safe to use breakpoints.
SYStem.Option.CoreStandBy On-the-fly breakpoint setup
On multi-core processors, only one of the cores starts to execute code right after reset. The other cores
remain in reset or disabled state. In this state it is not possible to set breakpoints or configure the core for
tracing. This option works around this limitation and makes breakpoints and tracing available right from the
first instruction executed. This option has impact on the real-time behavior. Releasing a secondary core from
reset / disable state will be delayed for a few milliseconds.
SYStem.Option.DCFREEZE Prevent data cache line load/flush in debug
mode
Default: OFF.
Format: SYStem.Option.CINTDebug [ON | OFF]
Format: SYStem.Option.CoreStandBy [ON | OFF]
Format: SYStem.Option.DCFREEZE [ON | OFF]
To Next Page
Loading...
Need help?
General
