EasyManuals Logo

Lauterbach TRACE32 User Manual

Lauterbach TRACE32
56 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #25 background imageLoading...
Page #25 background image
PQIII Debugger | 25
©
1989-2021 Lauterbach GmbH
SYStem.CONFIG Configure debugger according to target topology
The four parameters IRPRE, IRPOST, DRPRE, DRPOST are required to inform the debugger about the
TAP controller position in the JTAG chain, if there is more than one processor in the JTAG chain. The
information is required before the debugger can be activated e.g. by a SYStem.Up. See example below.
TriState has to be used if (and only if) more than one debugger are connected to the common JTAG port at
the same time. TAPState and TCKLevel define the TAP state and TCK level which is selected when the
debugger switches to tristate mode.
Jtag Informs the debugger about the position of the Test Access Ports (TAP) in
the JTAG chain which the debugger needs to talk to in order to access the
debug and trace facilities on the chip.
Format: SYStem.CONFIG <parameter> <number_or_address>
SYStem.MultiCore <parameter> <number_or_address> (deprecated)
<parameter>
(JTAG):
DRPRE
DRPOST
IRPRE
IRPOST
CHIPDRLENGTH <bits>
CHIPDRPATTERN [Standard | Alternate <pattern>]
CHIPDRPOST <bits>
CHIPDRPRE <bits>
CHIPIRLENGTH <bits>
CHIPIRPATTERN [Standard | Alternate <pattern>]
CHIPIRPOST<bits>
CHIPIRPRE <bits>
TAPState
TCKLevel
TriState
Slave
NOTE: When using the TriState mode, nTRST/JCOMP must have a pull-up resistor on the
target. In TriState mode, a pull-down is recommended for TCK, but targets with pull-
up are also supported.

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Lauterbach TRACE32 and is the answer not in the manual?

Lauterbach TRACE32 Specifications

General IconGeneral
Operating System Support (Host)Windows, Linux
ManufacturerLauterbach GmbH
CategoryDebug and Trace Tool
Supported ArchitecturesARM, Power Architecture, RISC-V, x86
InterfaceJTAG, SWD, Nexus, Aurora
FeaturesDebugging, tracing, multicore debugging
Host InterfaceUSB, Ethernet
IDE IntegrationEclipse
Scripting LanguagePractice
Power MeasurementYes (requires specific PowerProbe hardware)
Trace TechnologyInstruction Trace, Data Trace
License TypeFloating license, node-locked license available
Software CompatibilitySupports various compilers and toolchains

Related product manuals