PQIII Debugger | 19
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MESI States and Cache Status Flags
The data cache logic of Power Architecture cores is described as states of the MESI protocol. The debugger
displays the cache state using the cache line status flags valid, dirty and shared. The debugger also displays
additional status flags (e. g. locked) which can not be mapped to any of the MESI states.
State translation table:
Viewing Cache Contents
The cache contents can be viewed using the CACHE.DUMP command.
The meaning of the data fields in the CACHE.DUMP window os explained in the following table:
MESI state Flag
M (modified) V(alid) && D(irty)
E (exclusive) V(alid) && NOT D(irty)
S (shared) V(alid) && S(hared)
I (invalid) NOT V(alid)
Cache Command
L1 instruction cache CACHE.DUMP IC
L1 data dache CACHE.DUMP DC
L2 (unified cache) CACHE.DUMP L2
Data field Meaning
address Physical address of the cache line. The address is composed of
cache tag and set index.
set
way
Set and way index of the cache
v, d, s Status bits of the cache line v(alid), d(irty), s(hared)
# MESI state
l l(ocked).
00 04 08 ... Address offsets within cache line corresponding to the cached data
address (right field) Debug symbol assigned to address
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