PQIII Debugger | 26
©
1989-2021 Lauterbach GmbH
… DRPOST <bits> (default: 0) <number> of TAPs in the JTAG chain between the core of
interest and the TDO signal of the debugger. If each core in the system
contributes only one TAP to the JTAG chain, DRPRE is the number of
cores between the core of interest and the TDO signal of the debugger.
… DRPRE <bits> (default: 0) <number> of TAPs in the JTAG chain between the TDI signal
of the debugger and the core of interest. If each core in the system
contributes only one TAP to the JTAG chain, DRPOST is the number of
cores between the TDI signal of the debugger and the core of interest.
… IRPOST <bits> (default: 0) <number> of instruction register bits in the JTAG chain
between the core of interest and the TDO signal of the debugger. This is
the sum of the instruction register length of all TAPs between the core of
interest and the TDO signal of the debugger.
… IRPRE <bits> (default: 0) <number> of instruction register bits in the JTAG chain
between the TDI signal and the core of interest. This is the sum of the
instruction register lengths of all TAPs between the TDI signal of the
debugger and the core of interest.
CHIPDRLENGTH
<bits>
Number of Data Register (DR) bits which needs to get a certain BYPASS
pattern.
CHIPDRPATTERN
[Standard | Alter-
nate <pattern>]
Data Register (DR) pattern which shall be used for BYPASS instead of
the standard (1...1) pattern.
CHIPIRLENGTH
<bits>
Number of Instruction Register (IR) bits which needs to get a certain
BYPASS pattern.
CHIPIRPATTERN
[Standard | Alter-
nate <pattern>]
Instruction Register (IR) pattern which shall be used for BYPASS instead
of the standard pattern.
TAPState (default: 7 = Select-DR-Scan) This is the state of the TAP controller when
the debugger switches to tristate mode. All states of the JTAG TAP
controller are selectable.
TCKLevel (default: 0) Level of TCK signal when all debuggers are tristated.
TriState (default: OFF) If more than one debugger share the same JTAG port, this
option is required. The debugger switches to tristate mode after each
JTAG access. Then other debuggers can access the port.
Slave (default: OFF) If more than one debugger share the same JTAG port, all
except one must have this option active. Only one debugger - the
“master” - is allowed to control the signals nTRST and nSRST (nRESET).
To Next Page
Loading...
Need help?
General
