Lauterbach TRACE32 User Manual

PQIII Debugger | 4
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1989-2021 Lauterbach GmbH
CPU specific BenchMarkCounter Commands ................................................................ 48
BMC.FREEZE Freeze counters while core halted 48
BMC.<counter>.FREEZE Freeze counter in certain core states 48
BMC.<counter>.SIZE No function 49
CPU specific TrOnchip Commands .................................................................................50
TrOnchip.CONVert Adjust range breakpoint in on-chip resource 50
TrOnchip.DISable Disable NEXUS trace register control 50
TrOnchip.ENable Enable NEXUS trace register control 51
TrOnchip.RESet Reset on-chip trigger settings 51
TrOnchip.Set Enable special on-chip breakpoints 52
TrOnchip.VarCONVert Adjust HLL breakpoint in on-chip resource 53
TrOnchip.state View on-chip trigger setup window 54
MPC85XX/QorIQ Specific On-chip Trace Settings ......................................................... 55
Onchip.Mode.IFSel Select interface to be traced 55
JTAG Connector ................................................................................................................ 56
Mechanical Description 56
JTAG Connector MPC85XX (COP) 56

Lauterbach TRACE32 Specifications

General

Operating System Support (Host)	Windows, Linux
Manufacturer	Lauterbach GmbH
Category	Debug and Trace Tool
Supported Architectures	ARM, Power Architecture, RISC-V, x86
Interface	JTAG, SWD, Nexus, Aurora
Features	Debugging, tracing, multicore debugging
Host Interface	USB, Ethernet
IDE Integration	Eclipse
Scripting Language	Practice
Power Measurement	Yes (requires specific PowerProbe hardware)
Trace Technology	Instruction Trace, Data Trace
License Type	Floating license, node-locked license available
Software Compatibility	Supports various compilers and toolchains