PPC600 Family Debugger | 22
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1989-2022 Lauterbach
(*) Depending on the debugger configuration, the coherency of the instruction cache will not be achieved by
updating the instruction cache, but by invalidating the instruction cache. See “SYStem.Option ICFLUSH
Invalidate instruction cache before go/step” (debugger_ppc600.pdf) for details.
MESI States
The cache logic of e300, e600, e700 and PPC603e based cores is described as MESI states. This MESI
state are represented in the CPU as the flags Valid and Dirty. The debugger will display both MESI state and
the status flag representation.
State translation table:
MESI state Flag
M (modified) Valid && Dirty
E (exclusive) Valid && NOT Dirty
S (shared) Shared
I (invalid) NOT Valid
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