PPC600 Family Debugger | 28
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1989-2022 Lauterbach
SYStem.CONFIG Configure debugger according to target topology
The four parameters IRPRE, IRPOST, DRPRE, DRPOST are required to inform the debugger about the
TAP controller position in the JTAG chain, if there is more than one core in the JTAG chain (e.g. ARM +
DSP). The information is required before the debugger can be activated e.g. by a SYStem.Up. See Daisy-
chain Example.
For some CPU selections (SYStem.CPU) the above setting might be automatically included, since the
required system configuration of these CPUs is known.
TriState has to be used if several debuggers (“via separate cables”) are connected to a common JTAG port
at the same time in order to ensure that always only one debugger drives the signal lines. TAPState and
TCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristate
mode. Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down
resistor, other trigger inputs need to be kept in inactive state.
Format: SYStem.CONFIG <parameter> <number_or_address>
SYStem.MultiCore <parameter> <number_or_address> (deprecated)
<parameter>: CORE <core>
<parameter>:
(JTAG):
DRPRE <bits>
DRPOST <bits>
IRPRE <bits>
IRPOST <bits>
CHIPDRLENGTH <bits>
CHIPDRPATTERN [Standard | Alternate <pattern>]
CHIPDRPOST <bits>
CHIPDRPRE <bits>
CHIPIRLENGTH <bits>
CHIPIRPATTERN [Standard | Alternate <pattern>]
CHIPIRPOST<bits>
CHIPIRPRE <bits>
TAPState <state>
TCKLevel <level>
TriState [ON | OFF]
Slave [ON | OFF]
Multicore debugging is not supported for the DEBUG INTERFACE (LA-7701).
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