Lauterbach TRACE32-ICD User Manual

PPC600 Family Debugger | 29
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1989-2022 Lauterbach
CORE For multicore debugging one TRACE32 PowerView GUI has to be started
per core. To bundle several cores in one processor as required by the
system this command has to be used to define core and processor
coordinates within the system topology.
Further information can be found in SYStem.CONFIG.CORE.
… DRPOST <bits> (default: 0) <number> of TAPs in the JTAG chain between the core of
interest and the TDO signal of the debugger. If each core in the system
contributes only one TAP to the JTAG chain, DRPRE is the number of
cores between the core of interest and the TDO signal of the debugger.
… DRPRE <bits> (default: 0) <number> of TAPs in the JTAG chain between the TDI signal
of the debugger and the core of interest. If each core in the system
contributes only one TAP to the JTAG chain, DRPOST is the number of
cores between the TDI signal of the debugger and the core of interest.
… IRPOST <bits> (default: 0) <number> of instruction register bits in the JTAG chain
between the core of interest and the TDO signal of the debugger. This is
the sum of the instruction register length of all TAPs between the core of
interest and the TDO signal of the debugger.
… IRPRE <bits> (default: 0) <number> of instruction register bits in the JTAG chain
between the TDI signal and the core of interest. This is the sum of the
instruction register lengths of all TAPs between the TDI signal of the
debugger and the core of interest.
CHIPDRLENGTH
<bits>
Number of Data Register (DR) bits which needs to get a certain BYPASS
pattern.
CHIPDRPATTERN
[Standard | Alter-
nate <pattern>]
Data Register (DR) pattern which shall be used for BYPASS instead of
the standard (1...1) pattern.
CHIPIRLENGTH
<bits>
Number of Instruction Register (IR) bits which needs to get a certain
BYPASS pattern.
CHIPIRPATTERN
[Standard | Alter-
nate <pattern>]
Instruction Register (IR) pattern which shall be used for BYPASS instead
of the standard pattern.
TAPState (default: 7 = Select-DR-Scan) This is the state of the TAP controller when
the debugger switches to tristate mode. All states of the JTAG TAP
controller are selectable.
TCKLevel (default: 0) Level of TCK signal when all debuggers are tristated.

Lauterbach TRACE32-ICD Specifications

General

Brand	Lauterbach
Model	TRACE32-ICD
Category	Computer Accessories
Language	English