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TRACE32-ICD
Lauterbach TRACE32-ICD User Manual
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PPC600 Family Debugger | 65
©
1989-2022
Lauterbach
T
echnical Data
64
Table of Contents
PPC600 Family Debugger
1
Table of Contents
2
Introduction
6
Brief Overview of Documents for New Users
6
Warning
7
Signal Level
7
ESD Protection
7
Target Design Requirement/Recommendations
8
General
8
Quick Start
9
Troubleshooting
11
Problems with Memory Access
12
Faq
12
Configuration
13
System Overview
13
Powerpc 600 Family Specific Implementations
14
Breakpoints
14
Software Breakpoints
14
Software Breakpoint Handling
15
On-Chip Breakpoints
17
Software Breakpoints in Interrupt Handlers
18
Breakpoints in FLASH/ROM
18
Breakpoints on Physical or Virtual Addresses
18
Examples for Breakpoints
19
Software Breakpoints
19
On-Chip Program Address Breakpoints
19
On-Chip Data Address Breakpoints
19
Access Classes
20
Access Classes to Memory and Memory Mapped Resources
20
Access Classes to Other Addressable Core and Peripheral Resources
21
Cache
21
Memory Coherency
21
MESI States
22
Little Endian Operation
23
CPU Specific System Commands
24
System.bdmclock
24
Set JTAG Frequency
24
System.cpu
24
Select the CPU Type
24
System.lock
25
Lock and Tristate the Debug Port
25
System.memaccess
25
Real-Time Memory Access (Non-Intrusive)
25
System.mode
26
Select Operation Mode
26
System.config.state
27
Display Target Configuration
27
System.config
28
Configure Debugger According to Target Topology
28
Daisy-Chain Example
31
Tapstates
32
System.config.chkstpin Control Pin 8 of Debug Connector
32
System.config.core Assign Core to TRACE32 Instance
33
System.config.driverstrength
34
Configure Driver Strength of TCK Pin
34
System.config.qack
34
Control QACK Pin
34
CPU Specific System Commands
35
System.option.base
35
Set Base Address for On-Chip Peripherals
35
System.option.bus32
36
Use 32-Bit Data-Bus Mode
36
System.option.config
36
Select RCW Configuration
36
System.option.dcread
37
Read from Data Cache
37
System.option.dualport
37
Implicitly Use Run-Time Memory Access
37
System.option.freeze Freeze Timebase When Core Halted
38
System.option.holdreset
39
Set Reset Hold Time
39
System.option.hook
39
Compare PC to Hook Address
39
System.option.hrcwoverride
40
Override HRCW on System.up
40
System.option.icflush
40
Invalidate Instruction Cache before Go/Step
40
System.option.icread
41
Read from Instruction Cache
41
System.option.imaskasm
41
Disable Interrupts While Single Stepping
41
System.option.imaskhll
41
Disable Interrupts While HLL Single Stepping
41
System.option.ip
42
Set MSR_IP Value for Breakpoints / System.up
42
System.option.littleend
42
True Little Endian Mode
42
System.option.memprotect
42
Enable Memory Access Safeguard
42
System.option.memspeed
43
Configure Memory Access Timing
43
System.option.mmuspaces
43
Separate Address Spaces by Space Ids
43
System.option.nodebugstop
44
Disable JTAG Stop on Debug Events
44
System.option.notrap
45
Use Alternative Software Breakpoint Instruction
45
System.option.overlay
46
Enable Overlay Support
46
System.option.parity
46
Generate Parity on Memory Access
46
System.option.pintdebug
47
Program Interrupt Debugging
47
System.option.ppclittleend
47
PPC Little Endian Mode
47
System.option.pte
48
Evaluate PTE Table for Address Translation
48
System.option.resetbehavior
48
Set Behavior When Target Reset Detected
48
System.option.resetmode
49
Select Reset Mode for System.up
49
System.option.slowreset
49
Relaxed Reset Timing
49
System.option.stepsoft
50
Use Alternative Method for ASM Single Step
50
System.option.waitreset
51
Set Reset Wait Time
51
System.option.watchdog
52
Leave Software Watchdog Enabled
52
CPU Specific MMU Commands
53
Mmu.dump
53
Page Wise Display of MMU Translation Table
53
Mmu.list
55
Compact Display of MMU Translation Table
55
Mmu.scan
57
Load MMU Table from CPU
57
Mmu.set
58
Write MMU TLB Entries to CPU
58
CPU Specific Benchmarkcounter Commands
59
Bmc.<Counter>.Freeze
59
Freeze Counter in Certain Core States
59
BMC.FREEZE Freeze Counters While Core Halted
60
CPU Specific Tronchip Commands
61
Tronchip.disable
61
Disable Debug Register Control
61
Tronchip.enable
61
Enable Debug Register Control
61
Tronchip.convert
61
Adjust Range Breakpoint in On-Chip Resource
61
Tronchip.varconvert
62
Adjust Complex Breakpoint in On-Chip Resource
62
Tronchip.reset
62
Reset On-Chip Trigger Settings
62
Tronchip.state
62
Display On-Chip Trigger Window
62
Tronchip.tenable
62
Set Filter for the Trace
62
Tronchip.toff
63
Switch the Sampling to the Trace to off
63
Tronchip.ton
63
Switch the Sampling to the Trace to "ON
63
Tronchip.ttrigger
63
Set a Trigger for the Trace
63
Mechanical Description
64
JTAG/COP Connector Ppc603E/700/Mpc8200
64
Technical Data
65
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Lauterbach TRACE32-ICD Specifications
General
Brand
Lauterbach
Model
TRACE32-ICD
Category
Computer Accessories
Language
English
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