Lime Microsystems LMS7002MR3 - Default Chapter; Table of Contents

1
Contents
1. Serial Port Interface ............................................................................................................ 3
1.1 Description ................................................................................................................. 3
2. LMS7002Mr3 Memory Map Description.......................................................................... 5
2.1 LMS7002Mr3 Memory Map ...................................................................................... 5
2.2 General Control, LimeLight
TM
and IO Cell Configuration Memory ......................... 8
2.3 NCO Configuration Memory ................................................................................... 17
2.4 TxTSP(A/B) Configuration Memory ....................................................................... 20
2.5 RxTSP(A/B) Configuration Memory ....................................................................... 23
2.6 RX/TX GFIR1/GFIR2 Coefficient Memory ............................................................ 26
2.7 RX/TX GFIR3 Coefficient Memory ........................................................................ 27
2.8 RFE(1, 2) Configuration Memory ............................................................................ 28
2.9 RBB(1, 2) Configuration Memory ........................................................................... 32
2.10 TRF(1, 2) Configuration Memory ............................................................................ 35
2.11 TBB(1, 2) Configuration Memory ........................................................................... 37
2.12 TRX Gain Configuration Memory ........................................................................... 39
2.13 AFE Configuration Memory .................................................................................... 41
2.14 BIAS Configuration Memory ................................................................................... 42
2.15 SXR, SXT Configuration Memory .......................................................................... 43
2.16 CGEN Configuration Memory ................................................................................. 47
2.17 XBUF Configuration Memory ................................................................................. 50
2.18 LDO Configuration Memory ................................................................................... 51
2.19 EN_DIR Configuration Memory ............................................................................. 60
2.20 SXR, SXT and CGEN BIST Configuration Memory .............................................. 61
2.21 CDS Configuration Memory .................................................................................... 62
2.22 mSPI Configuration Memory ................................................................................... 64
2.23 DC Calibration Configuration Memory ................................................................... 65
2.24 RSSI, PDET and TEMP measurement Configuration Memory .............................. 70
2.25 Analog RSSI Calibration Configuration Memory ................................................... 72
3. SPI Procedures ................................................................................................................... 73
A1.1 SPI READ/WRITE Pseudo Code ............................................................................ 73
4. Control Block Diagrams ................................................................................................... 75
A2.1 RFE Control Diagrams ............................................................................................. 76
A2.2 RBB Control Diagrams ............................................................................................ 78
A2.3 TRF Control Diagrams ............................................................................................. 80
A2.4 TBB Control Diagrams ............................................................................................ 82
A2.5 AFE Control Diagram .............................................................................................. 84
A2.6 BIAS Control Diagram ............................................................................................. 85
A2.7 SXR and SXT Control Diagrams ............................................................................. 86
A2.8 CGEN Control Diagram ........................................................................................... 88
A2.9 XBUF Control Diagram ........................................................................................... 89
A2.10 LDOs Control Diagram ........................................................................................ 90
A2.11 CDS Control Diagram .......................................................................................... 91
A2.12 IO Cell Control Diagram ...................................................................................... 91
A2.13 TxTSP(A/B) Control Diagram ............................................................................. 92
A2.14 RxTSP(A/B) Control Diagram ............................................................................. 93
A2.15 SXR, SXT and CGEN BIST Control Diagram .................................................... 94