Lime Microsystems LMS7002MR3 - DC Calibration Configuration Memory

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2.23 DC Calibration Configuration Memory
The block diagrams of the DC calibration modules are shown in Figure 28. The tables in this
chapter describes control registers of DC calibration modules.
Table 24: DC calibration configuration memory
Address (15 bits)
Bits
Description
0x05C0
15
14 – 8
7
6
5
4
3
2
1
0
DCMODE: Control for the DC offset calibration mode.
0 – Manual. In this mode, receiver DC offset can be changed manualy by
using registers 0x010D[6] and 0x010E[13:0] (default)
1 – Automatic. In this mode, receiver and transmitter DC offset DACs and
comparators are controlled from addresses 0x05C0–0x05CC. Individual
automatic DC offset calibration routines can be started with control
located in register 0x05C1[7:0] .
Reserved
PD_DCDAC_RXB. Power down control for receiver channel B DC offset cancelation
DAC:
0 – block active
1 – block powered down (default)
PD_DCDAC_RXA. Power down control for receiver channel A DC offset cancelation
DAC:
0 – block active
1 – block powered down (default)
PD_DCDAC_TXB. Power down control for transmiter channel B DC offset
cancelation DAC:
0 – block active
1 – block powered down (default)
PD_DCDAC_TXA. Power down control for transmitter channel A DC offset
cancelation DAC:
0 – block active
1 – block powered down (default)
PD_DCCMP_RXB. Power down control for receiver channel B comparator, used in
automatic DC offset calibration routine:
0 – block active
1 – block powered down (default)
PD_DCCMP_RXA. Power down control for receiver channel A comparator, used in
automatic DC offset calibration routine:
0 – block active
1 – block powered down (default)
PD_DCCMP_TXB. Power down control for transmitter channel B comparator, used
in automatic DC offset calibration routine:
0 – block active
1 – block powered down (default)
PD_DCCMP_TXA. Power down control for transmitter channel A comparator, used
in automatic DC offset calibration routine:
0 – block active
1 – block powered down (default)
Default: 00000000 11111111