TSTIN_TBB_(1, 2)[1:0]: This control selects where the input test signal
(vinp/n_aux_bbq/i) is routed to as well as disabling the route.
0 – Disabled. Test signal is not routed any where. (default)
1 – Test signal is routed to the input of the Highband Filter.
2 – Test signal is routed to the input of the LowBand Filter.
3 - Test signal is routed to the input of the current amplifier.
BYPLADDER_TBB_(1, 2): This signal by passes the LPF ladder of TBB and directly
connects the output of current amplifier to the null port of the real pole stage of TBB
low pass filter.
1 – bypass is active
0 – bypass is inactive (default)
CCAL_LPFLAD_TBB_(1, 2)[4:0]: A common control signal for all the capacitor
banks of TBB filters (including the ladder, real pole, and the high band biquad). It is
the calibrated value of the banks control that sets the value of the banks' equivalent
capacitor to their respective nominal values. Default: 16
RCAL_LPFS5_TBB_(1, 2)[7:0]: This controls the value of the equivalent resistance
of the resistor banks of the real pole filter stage (of the low band section) of the
transmitter base band (TBB). Following is a nominal values table that are corrected
for any process variation after calibration:
If >5.5MHz 200 otherwise 76. Default: 76
Default: 00010000 01001100
Reserved
RESRV_TBB_(1, 2)[2:1]: Reserved for future use. Default: 0
R5_LPF_BYP_TBB_(1, 2): Bypasses LPFS5_TBB low pass real-pole filter capacitor
banks. Stage must remain active when bypass is enabled.
0 – Normal LPFS5_TBB low pass real-pole filter operation. (default)
1 – LPFS5_TBB low pass real-pole filter acts as a buffer.
Default: 00000000 00000000
RFE modules. These registers are only active if register TRX_GAIN_SRC (0x0081[15]) is set
to 1. If TRX_GAIN_SRC is 0, then these registers are controlled from their usual addresses.
To Next Page
Loading...