Lime Microsystems LMS7002MR3 - CDS Configuration Memory

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2.21 CDS Configuration Memory
The block diagram of the Clock Distribution System (CDS) module is shown in Figure 20.
The tables in this chapter describe the control registers of CDS module.
Table 22: CDS configuration memory
Address (15 bits)
Bits
Description
0x00AD
15 – 14
13 – 12
11 – 10
9
8
7
6
5
4
3
2
1
0
CDS_MCLK2[1:0]: MCLK2 clock delay.
00 – delay by 400ps (default)
01 – delay by 500ps
10 – delay by 600ps
11 – delay by 700ps
CDS_MCLK1[1:0]: MCLK1 clock delay.
00 – delay by 400ps (default)
01 – delay by 500ps
10 – delay by 600ps
11 – delay by 700ps
Reserved
CDSN_TXBTSP: TX TSPB clock inversion control.
0 – Clock is inverted
1 – Clock is not inverted (default)
CDSN_TXATSP: TX TSPA clock inversion control.
0 – Clock is inverted
1 – Clock is not inverted (default)
CDSN_RXBTSP: RX TSPB clock inversion control.
0 – Clock is inverted
1 – Clock is not inverted (default)
CDSN_RXATSP: RX TSPA clock inversion control.
0 – Clock is inverted
1 – Clock is not inverted (default)
CDSN_TXBLML: TX LMLB clock inversion control.
0 – Clock is inverted
1 – Clock is not inverted (default)
CDSN_TXALML: TX LMLA clock inversion control.
0 – Clock is inverted
1 – Clock is not inverted (default)
CDSN_RXBLML: RX LMLB clock inversion control.
0 – Clock is inverted
1 – Clock is not inverted (default)
CDSN_RXALML: RX LMLA clock inversion control.
0 – Clock is inverted
1 – Clock is not inverted (default)
CDSN_MCLK2: MCLK2 clock inversion control.
0 – Clock is inverted
1 – Clock is not inverted (default)
CDSN_MCLK1: MCLK1 clock inversion control.
0 – Clock is inverted
1 – Clock is not inverted (default)
Default: 00000011 11111111