Lime Microsystems LMS7002MR3 - 1 Serial Port Interface; Description

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Serial Port Interface
1.1 Description
The functionality of LMS7002Mr3 transceiver is fully controlled by a set of internal registers
which can be accessed through a serial SPI port interface. Both write and read operations are
supported. The serial SPI port can be configured to run in 3 or 4 wire mode with the following
pins used:
 SEN SPI serial port enable, active low, output from master;
 SCLK SPI serial clock, output from master;
 SDIO SPI serial data in/out (Master Output Slave Input (MOSI) / Master
Input Slave Output (MISO)) in 3 wire mode, serial data input (MOSI) in 4 wire mode;
 SDO SPI serial data out (MISO) in 4 wire mode, don’t care in 3 wire mode.
SPI serial port key features:
 Operating as slave;
 Operating in SPI Mode 0: data is captured on the clock's rising edge, while data is
shifted on the clock's falling edge (i.e. clock polarity CPOL = 0 and clock phase
CPHA = 0);
 32 serial clock cycles are required to complete write operation;
 32 serial clock cycles are required to complete read operation;
 Multiple write/read operations are possible without toggling serial enable signal.
All configuration registers are 16-bit wide. Write/read sequence consists of 16-bit instruction
followed by 16-bit data to write or read. MSB of the instruction bit stream is used as SPI
command where CMD = 1 for write and CMD = 0 for read. Next 4 bits are reserved
(Reserved[3:0]) and must be zeroes. Next 5 bits represent block address (Maddress[4:0]) since
LMS7002Mr3 configuration registers are divided into logical blocks as shown in
Table 1. Remaining 6 bits of the instruction are used to address particular registers
(Reg[5:0]) within the block as described in Section 2. Maddress and Reg compiles global 11-