Lime Microsystems LMS7002MR3 - 2 Lms7002 Mr3 Memory Map Description; Lms7002 Mr3 Memory Map

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LMS7002Mr3 Memory Map Description
2.1 LMS7002Mr3 Memory Map
All the LMS7002Mr3 configuration space is accessible via serial SPI interface. All the
configuration space is divided to logical block types:
 Other
 Top
 TRX
 TX
 RX
LMS7002Mr3 chip is MIMO, hence it have two channels called A and B. So, some
analogue/digital modules appears in MIMO channel A as well as B (from TRX, TX and RX
blocks). The rest of moduleMr3s (from Other and Top logical block types) are controlled only
from one memory block. All the logical blocks are summarized in
Table 1.
To save the addressing space and speed-up write operation the following trick is used
for the TRX, TX and RX logical block types. There is a register called MAC[1:0] (address of
this register is 0x0020[1:0]) which selects MIMO channel A or/and B. MIMO channel select
logic depends on MAC[1:0] register as described below (see Figure 1 for reference):
 11 – SPI write operation possible only. The same data are written to the A and B
MIMO channels at the same time. Note, that read operation will corrupt read data
when MAC[1:0] is set to "11".
 01 – SPI read/write operation possible. Data may be written to or read from the MIMO
channel A only.
 10 – SPI read/write operation possible. Data may be written to or read from the MIMO
channel B only.