Lime Microsystems LMS7002MR3 - SXR, SXT Configuration Memory

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2.15 SXR, SXT Configuration Memory
The block diagrams of the SXR and SXT modules are shown in Figure 15 and Figure 16 respectively.
The tables in this chapter describe the control registers of SXR and SXT modules.
Table 16: SXT (SXR) configuration memory
Address (15 bits)
Bits
Description
0x011C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET_N_(SXR, SXT): Resets SX. A pulse should be used in the start-up to reset
0 – Reset
1 – Normal operation (default)
SPDUP_VCO_(SXR, SXT): Bypasses the noise filter resistor for fast settling time. It
should be connected to a 1uS pulse
0 – speed up disabled (noise filter resistor active) (default)
1 – speed up enabled (noise filter resistor shorted)
BYPLDO_VCO_(SXR, SXT): Controls the bypass signal for the SX LDO
0 – LDO active
1 – LDO bypassed (input/output of the SX LDO shorted) (default)
EN_COARSEPLL_(SXR, SXT): Enable signal for coarse tuning block
0 – Coarse tuning disabled (default)
1 – Coarse tuning enabled
CURLIM_VCO_(SXR, SXT): Enables the output current limitation in the VCO
regulator
0 – Current limit disabled
1 – Current limit enabled (default)
EN_DIV2_DIVPROG_(SXR, SXT): Enables additional DIV2 prescaler at the input of
the Programmable divider. The core of programmable divider in the SX feedback
divider works up to 5.5GHz. For FVCO>5.5GHz, the prescaler is needed to lower
the input frequency to DIVPROG_SX. Shadow register.
0 – DIVPROG input =
Fvco [Fvco=Fref*((INT_SDM_SX+4)+FRAC_SDM)
1 – DIVPROG input =
Fvco/2 [Fvco=2*Fref*((INT_SDM_SX+4)+FRAC_SDM) (default)
EN_INTONLY_SDM_(SXR, SXT): Enables INTEGER-N mode of the SX
0 – Frac-N mode (default)
1 – INT-N mode
EN_SDM_CLK_(SXR, SXT): Enables/Disables SDM clock. In INT-N mode or for
noise testing, SDM clock can be disabled
0 – SDM clock disabled
1 – SDM clock enabled (default)
PD_FBDIV_(SXR, SXT): Power down the feedback divider block.
0 – block active (default)
1 – block powered down
PD_LOCH_T2RBUF: Power down for LO buffer from SXT to SXR. To be active only
in the TDD mode. In TX part only!!!
0 – block active
1 – block powered down (default)
PD_CP_(SXR, SXT): Power down for Charge Pump
0 – block active (default)
1 – block powered down
PD_FDIV_(SXR, SXT): Power down for forward frequency divider and divider chain
of the LO chain.
0 – blocks active (default)
1 – blocks powered down
PD_SDM_(SXR, SXT): Power down for SDM
0 – block active (default)
1 – block powered down
PD_VCO_COMP_(SXR, SXT): Power down for VCO comparator
0 – block active (default)
1 – block powered down
PD_VCO_(SXR, SXT): Power down for VCO
0 – block active
1 – block powered down (default)
EN_G_(SXR, SXT): Enable control for all the SX power downs
0 – All SXT modules powered down
1 – All SXT modules controlled by individual power down registers
(default)
Default: 10101101 01000011