Lime Microsystems LMS7002MR3 - Page 48

44
Address (15 bits)
Bits
Description
0x011D
15 – 0
FRAC_SDM_(SXR, SXT)[15:0]: Fractional control of the division ratio LSB. Default:
1024
=2^20*[Fvco/(Fref * 2^ EN_DIV2_DIVPROG_(SXR, SXT)) –
int(Fvco/(Fref * 2^ EN_DIV2_DIVPROG_(SXR, SXT)))]
Default: 00000100 00000000
0x011E
15 - 14
13 – 4
3 – 0
Reserved
INT_SDM_(SXR, SXT)[9:0]: Controls Integer section of the division ratio
INT_SDM_(SXR, SXT) = int(Fvco/2^(EN_DIV2_DIVPROG_(SXR,
SXT))/Fref)-4 Default: 120
FRAC_SDM_(SXR, SXT)[19:16]: Fractional control of the division ratio MSB.
Default: 00000111 10000000
0x011F
15
14 – 12
11 – 9
8 – 6
5 – 3
2
1
0
Reserved
PW_DIV2_LOCH_(SXR, SXT)[2:0]: trims the duty cycle of DIV2 LOCH. Only works
when forward divider is dividing by at least 2 (excluding quadrature block division). If
in bypass mode, this does not work. Default: 3
PW_DIV4_LOCH_(SXR, SXT)[2:0]: trims the duty cycle of DIV4 LOCH. Only works
when forward divider is dividing by at least 4 (excluding quadrature block division). If
in bypass mode, this does not work. Default: 3
DIV_LOCH_(SXR, SXT)[2:0]: Controls the division ratio in the LOCH_DIV. There is
additional DIV/2 in the quadrature generator 
Flo = Fvco / divRatio_LOCH / 2
divRatio_LOCH = 2^(DIV_LOCH_SX)
Note: Value 111 not allowed.
Shadow register. Default: 1
TST_SX_(SXR, SXT)[2:0]: Controls the test mode of PLLs. TST signal lines are
shared between all PLLs (CGEN, RX and TX). Only one TST signal of any PLL
should be active at a given time.
0 – TST disabled; RSSI analog outputs enabled if RSSI blocks active and
when all PLL test signals are off (default)
1 – tstdo[0]=VCO/20 clock*; tstdo[1]=VCO/40 clock*; tstao = High
impedance;
2 – tstdo[0]=SDM clock; tstdo[1]= feedback divider output; tstao = VCO
tune through a 60kOhm resistor;
3 – tstdo[0]=Reference clock; tstdo[1]= feedback divider output; tstao =
VCO tune through a 10kOhm resistor;
4 – tstdo[0]= High impedance; tstdo[1]= High impedance; tstao = High
impedance;
5 – tstdo[0]=Charge pump Down signal; tstdo[1]=Charge pump Up signal;
tstao = High impedance;
6 – tstdo[0]= High impedance; tstdo[1]= High impedance; tstao = VCO
tune through a 60kOhm resistor;
7 – tstdo[0]= High impedance; tstdo[1]= High impedance; tstao = VCO
tune through a 10kOhm resistor;
if TST_SX[2]=1 --> VCO_TSTBUF active generating VCO_TST_DIV20
and VCO_TST_DIV40
* When EN_DIV2_DIVPROG_(SXR, SXT) is active, the division ratio must
be multiplied by 2 (40/80);
SEL_SDMCLK_(SXR, SXT): Selects between the feedback divider output and Fref
for SDM
0 – CLK CLK_DIV (default)
1 – CLK CLK_REF
SX_DITHER_EN_(SXR, SXT): Enabled dithering in SDM
0 – Disabled (default)
1 – Enabled
REV_SDMCLK_(SXR, SXT): Reverses the SDM clock
0 – (default)
1 – reversed (after INV)
Default: 00110110 01000000