Lime Microsystems LMS7002MR3 - Page 49

45
Address (15 bits)
Bits
Description
0x0120
15 – 8
7 – 0
VDIV_VCO_(SXR, SXT)[7:0]: Controls VCO LDO output voltage. Default: 185
Vout(VCO_LDO)=VDD18_VCO* [ (29.1/(29.1 + 233/(VDIV_VCO_SX+2)))]
185 --> Vout(VCO_LDO)=1.55V (VDD18_VCO=1.72)
ICT_VCO_(SXR, SXT)[7:0]: Scales the VCO bias current from 0 to 2.5xInom
Default: 128
Default: 10111001 10000000
0x0121
15 – 11
10 – 3
2 – 1
0
RSEL_LDO_VCO_(SXR, SXT)[4:0]: Set the reference voltage that supplies bias
voltage of switch-cap array and varactor. Default: 16
Vref=60uA * 180kOhm / RSEL_LDO_VCO
CSW_VCO_(SXR, SXT)[7:0]: coarse control of VCO frequency, 0 for lowest
frequency and 255 for highest. This control is set by SX_SWC_calibration. Shadow
register. Default: 128
SEL_VCO_(SXR, SXT)[1:0]: Selects the active VCO. It is set by
SX_SWC_calibration. Shadow register.
0 – VCOL
1 – VCOM
2 – VCOH (default)
3 – Not Valid
COARSE_START_(SXR, SXT): Control signal for coarse tuning algorithm
(SX_SWC_calibration). Default: 0
Default: 10000100 00000100
0x0122
15 – 14
13
12
11 – 6
5 – 0
RZ_CTRL_(SXR, SXT)[1:0]: Controls the PLL LPF zero resistor values:
0 – Rzero = 20kΩ (default)
1 – Rzero = 8kΩ
2 – Rzero = 4kΩ
3 – LPF resistors are in bypass mode (<100Ω)
CMPLO_CTRL_(SXR, SXT): Controls the SXR/SXT PLL VCO comparator low
treshold value:
0 – Low treshold is set to 0.18V (default)
1 – Low treshold is set to 0.1V
REVPH_PFD_(SXR, SXT): Reverse the pulses of PFD. It can be used to reverse
the polarity of the PLL loop (positive feedback to negative feedback). Default: 0
IOFFSET_CP_(SXR, SXT)[5:0]: Scales the offset current of the charge pump, 0--
>63. This current is used in Fran-N mode to create an offset in the CP response and
avoid the non-linear section. Default: 20
ioffset=0.243uA * IOFFSET_CP_SX
ioffset/ipulse=4/(INT_SDM_SX+4) [First estimation]
IPULSE_CP_(SXR, SXT)[5:0]: Scales the pulse current of the charge pump, 0-->63.
Default: 20
ipulse=2.312uA * IPULSE_CP_SX
Default: 00000101 00010100
0x0123
15
14
13
12
11 – 8
7 – 4
3 – 0
COARSE_STEPDONE_(SXR, SXT): Read only.
COARSEPLL_COMPO_(SXR, SXT): Read only.
VCO_CMPHO_(SXR, SXT): Compares Vtune value to a predefined value of
920mV. Read only register.
0 – Vtune voltage level is higher than CMPHO threshold voltage of 920mV
1 – Vtune voltage level is lower than CMPHO threshold voltage of 920mV
VCO_CMPLO_(SXR, SXT): Compares Vtune value to a predefined value of 180mV.
Read only register.
0 – Vtune voltage level is higher than CMPLO threshold voltage of 180mV
1 – Vtune voltage level is lower than CMPLO threshold voltage of 180mV
CP2_PLL_(SXR, SXT)[3:0]: Controls the value of CP2 (cap from CP output to GND)
in the PLL filter. Default: 6
cp2=CP2_PLL_SX*6*387fF
CP3_PLL_(SXR, SXT)[3:0]: Controls the value of CP3 (cap from VCO Vtune input to
GND) in the PLL filter. Default: 7
cp3=CP3_PLL_SX*6*980fF
CZ_(SXR, SXT)[3:0]: Controls the value of CZ (Zero capacitor) in the PLL filter.
Default: 11
cz=CZ_PLL_SX*8*5.88pF
Default: 00000110 01111011