Lime Microsystems LMS7002MR3 - Page 50

46
Address (15 bits)
Bits
Description
0x0124
15 – 11
10 – 5
4
3
2
1
0
RESRV_(SXR, SXT)[4:0]: Reserved. Default: 0
(For SXT only RESRV_SXR[0] connected to the output!)
Reserved
EN_DIR_(SXR, SXT): Enables direct control of PDs and ENs for SXR/SXT module.
0 – direct control disabled (default)
1 – direct control enabled
EN_DIR_RBB(1, 2): Enables direct control of PDs and ENs for RBB(1, 2) module.
0 – direct control disabled (default)
1 – direct control enabled
EN_DIR_RFE(1, 2): Enables direct control of PDs and ENs for RFE(1, 2) module.
0 – direct control disabled (default)
1 – direct control enabled
EN_DIR_TBB(1, 2): Enables direct control of PDs and ENs for TBB(1, 2) module.
0 – direct control disabled (default)
1 – direct control enabled
EN_DIR_TRF(1, 2): Enables direct control of PDs and ENs for TRF(1, 2) module.
0 – direct control disabled (default)
1 – direct control enabled
Default: 00000000 00000000