363-206-295
Circuit Pack Descriptions
7-28 Issue 1 December 1997
Control Circuitry 7
The BBG11 3DS3 circuit pack interfaces with the SYSCTL via the intra-shelf
control bus. Redundancy in the intra-shelf control bus assures the level of control
required to perform protection switching and alarming of a faulty circuit pack. The
BBG11 3DS3 provides maintenance elements for reporting the status of the
circuit pack, status of the incoming STS-1 and DS3 signals, as well as the circuit
pack inventory information (
CLEI
code, date of manufacture, etc.). These
maintenance elements are used by the SYSCTL for fault detection and isolation.
Conversely, the BBG11 3DS3 responds to control signals from the SYSCTL (such
as active and fault LED controls).
Timing Circuitry 7
The BBG11 3DS3 circuit pack derives its timing information from the recovered
DS3 clock of the DSX-3 incoming signal. In the transmit direction, a 44.736 MHz
clock is recovered from the incoming DS3 signal and is used to recover DS3 data.
In the receive direction, a smoothed 44.736 MHz clock is generated by a phase-
locked loop to accompany the DS3 signal extracted from the STS-1 payload.
In addition to the recovered DS3 clock, the BBG11 3DS3 circuit pack requires
STS-1 timing supplied by the TSI circuit pack, via the circuit pack edge connector,
from the backplane.
Protection Circuitry 7
Optional 1x1 nonrevertive BBG11 3DS3 circuit pack protection is provided. Switch
points for the STS-1 side of the BBG11 3DS3 are located on the TSI circuit packs.
Switch points for the DS3 side are implemented with relays on the 3DS3 circuit
pack. To ensure that the relays can be operated when the circuit pack fails, the
relay is controlled by the SYSCTL via the control interfaces. Also, if power to the
board is lost, the relay switches autonomously to the standby state. When a new
board is inserted, it defaults to the standby state until provisioned active by the
SYSCTL.
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