Major revisions of Matrox Solios 165
SOL6M4AE* 100 First shipping version.
101 Upgraded the PCI-X to PCIe bridge to a new version. This was a corrective
action. For more information, refer to product bulletin MIPB-67.
102 Modified the power-up sequence of the PCIe bridge. This was a corrective
action. For more information, refer to product bulletin MIPB-77.
103 Moved to secondary source for A/D. This was done to ensure availability.
104 Improved product packaging.
105 Replaced a pull-up resistor so that stronger PCIe interrupt signals could be
transmitted. This was a preventive action.
106
Changed the default acquisition firmware.
1
107 Upgraded the PCI-X to PCIe bridge to a new version. This was done to
ensure availability.
SOL6M4A30546* 200 First shipping version.
201 Added termination resistors to the interface of the Processing FPGA. This
was a corrective action.
202 Moved to secondary source for A/D. This was done to ensure availability.
203 Improved product packaging.
204 Added a JTAG connector that can be used to validate an FPGA
configuration loaded in the Processing FPGA. This was done to enhance
the feature set.
205 Moved to primary source for A/D. This was done to ensure availability.
SOL6M4AE30546* 100 First shipping version.
101 Replaced a pull-up resistor so that stronger PCIe interrupt signals could be
transmitted. This was a preventive action.
102 Removed termination resistors from the QDRII SRAM interface. This was a
corrective action.
103 Upgraded the PCI-X to PCIe bridge to a new version. This was done to
ensure availability.
1. Note that MIL automatically detects the version of the firmware and updates it if necessary.
RoHS-compliant versions of Matrox Solios eA/XA
Part number Version Description
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