Chapter 8
111
Flexi Line
Default value
The default value defines how a bit is affected by a station:
A bit with the default value High is set to 1 (logic status high) if all stations signal a
1 for this bit (logical AND). As soon as only one station sets the bit to the logic
status low, the bit is set to 0.
A bit with the default value Low is set to 0 (logic status low) if all stations signal a
0 for this bit (logical OR). As soon as only one station sets the bit to the logic
status high, the bit is set to 1.
Activation and deactivation of individual bits
You can deactivate bits that are not required by not assigning a name to these bits.
Deactivated bits are no longer available or shown in the logic editor or in the
diagnostics. However, the size of the process image is not affected by this change.
8.2.3 Flexi Line checksum (CRC)
The checksum is required so that the stations in a Flexi Line system can
communicate with each other. All stations in a Flexi Line system must have an
identical checksum. This ensures that only stations that belong to the same Flexi
Line system can communicate with each other. If a different checksum is detected in
a Flexi Line system, then all connected stations will change to the “Error on the Flexi
Line bus” mode (Line LED flashes
Red/green at 2 Hz).
The checksum is calculated from the following settings:
size of the process image and maximum cable length
update rate
range of each byte
default value of each byte
first part of the revision number
The minor revision number as well as the names you have assigned to bits, bytes
and the process image itself do not affect the checksum.
If the process image is changed on any station such that the checksum changes,
then you must transfer this new image to all other stations. In this way you will set
the checksum in all stations to the same value.
Otherwise there will be different checksums in the Flexi Line system such that the
safety communication between the stations cannot be established.
The checksum is part of the configuration that is saved in the memory plug for each
CPU3 module connected.
Note
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