NEC NC1600C - Page 225

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8-20
CIRCUIT DESCRIPTION
Signal Name Description I/O Type
SAT_[R/G/B] CLK_P/N Output Pixel Clock? 150MHz O 2.5 LVDS
SAT_[R/G/B] DATA_P/N (15:0) Output Pixel/Control Data O 2.5 LVDS
Video sync signals (Vsync, Hsync &
Actdata) are embedded in the 16 bit
data word
SAT_[R/G/B]_TXDATA_P/N Output register and setup control data O 2.5 LVDS
SAT_[R/G/B]_RXCLK_P/N Input data clock I 2.5 LVDS
SAT_[R/G/B]_RXDAT_P/N Input register and setup control data I 2.5 LVDS
SAT_[R/G/B]_LVDS_SPARE (1:0) Spare I/O signal lines. LVDS capable. I/O 2.5 LVDS
Currently not used.
SAT_[R/G/B]_LTTL_SPARE (1:0) Spare I/O signal lines. LVTTL. I/O LVTTL
Currently not used.
SAT_[R/G/B]_POWERGOOD Power status to Satellite O LVTTL
SAT_[R/G/B]_RESETZ Hardware Reset to Satellite O LVTTL
1-3. Satellite Data Interface (Red, Green, Blue)
Signal Name Description I/O Type
SAT_[R/G/B] CCLK FPGA Data Clock? used to time D_IN O LVCMOS
output during configuration.
SAT_[R/G/B]_D_IN FPGA Configuration Data? serial data O LVCMOS
output used to configure the Satellite
FPGA device.
SAT_[R/G/B]_DONE FPGA Configuration Done? indicates I LVCMOS
completion of device configuration.
SAT_[R/G/B]_INIT_B FPGA Init Pin? indicates whether a CRC I LVCMOS
error occurred during configuration :
0 = CRC error
1 = No CRC error
SAT_[R/G/B]_PROG_B FPGA Full-chip reset (Active LOW). O LVCMOS
1-4. Satellite FPGA Programming Interface