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8-19
CIRCUIT DESCRIPTION
FFIB PWB (FPGA Formatter Interface Board)
PWC-4683
In the Cinema circuit, the FFIB PWB enters the video data of the VIDEO processor and the SOFTWARE processor
in the LVTTL (3.3V) 16-bit EVEN/ODD format. After passing through various functional processing of Item 1
below, the data are transmitted to the FSB in the LVDS (2.5V) 16-pair format.
In the bootstrapping mode, configuration control is also carried out for each FSB.
Signal Name Description I/O Type
MB_RESETZ Hardware Reset I LVTTL
MB_POWERGOOD Main Power Status I LVTTL
Signal Name Description I/O Type
FCLK Pixel Clock I LVTTL
O/E [R/G/B] (15:0) Video Data, Odd/Even I LVTTL
O/E [R/G/B]_SIGN Video Data, Odd/Even Sign I LVTTL
O/E [R/G/B]_RSVD Video Data, Odd/Even Reserved 1 LVTTL
MB_ACTDATA Input Active Data I LVTTL
MB_VSYNCZ Input Vertical Sync I LVTTL
MB_HSYNCZ Input Horizontal Sync I LVTTL
MB_OLCATE Input Overlay Active Even I LVTTL
MB_OLACTO Input Overlay Active Odd I LVTTL
MB_SYNCVAL Input Sync Vaild I LVTTL
MB_3D_SYNC_IN 3D Input Reference I LVTTL
MB_3D_SYNC_OUT 3D Output reference O LVTTL
1. Electrical Interface
1-1. Intialzatopm
1-2. Main Data Interface