“Confidential, Do Not Duplicate without written authorization from NEC.”
8-25
CIRCUIT DESCRIPTION
3. Video output
In Sil1160 the parallel signals input from EP2C35F672 are converted to TMDS signals which are output to
Output-A (M6503) and Output-B (M6502) and from which the signals are each transmitted to the DVI ports of
TI at the following stage.
4. EDID
This board is not equipped with EDID ROM.
The DDC line (clock and data) is connected directly across Input-Output of the DVI connector on the board
and permits access to EDID ROM on the Cinema system Interface board connected at the following stage.
5. Configuration
IC6504 (EP2C35F672) is an FPGA and thus can be configured from IC6511 (EPCS16Sl16N) at the time of
power-on.
6. Power Supply
As a power supply both 3.3 and 5 volts are supplied via connector PODO (S5B-PH) from DIV PWB.
An I/O system power of 3.3 volts for each device is directly supplied.
A core supply of 1.2 volt for IC6504 is supplied after being converted from 5 volts by IC6512 (SC4519ST).
7. Equalizer
IC6502 and IC6503 (both are Sil1161) have the equalizing function that permits transmission of UXGA with
a cable of up to 15 meters (usually a cable of 2 meters at best).
In actual evaluation it has been verified that a 10-meter cable from Japan Avionics can be used.
The setting of this function is possible only for service and PC- or tablet-controlled.
Setting will be made for Sil1161 by I2C from CPU PWB via connector POTY (S6B-ZR).
Since Sil1161 has only one SLAVE address, switching is made by IC6509 and IC6510 (both are NC7WB66K8X)
as follows:
#1: I2C Clock
#2: I2C Data
#3: I2C CTLA
#4: I2C CTLB
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