Table 9. Capacitor recommendations to be placed near i.MX8 QM
2
(continued)
Checkbox Supply 1 µF
2.2
µF
22 µF 100 µF Notes
VDD_M1P8_CAP --- 1 --- --- Placed under the BGA package.
VREFH_ADC VDD_ANA0_1P8_n
VDD_ADC_1P8
VDD_MIPI_CSIn_1P8
VDD_MIPI_DSIn_1P8
VDD_LVDSn_1P8 VDD_MLB_1P8
(Note 4)
VDD_PCIEn_PLL_1P8
VDD_PCIE_SATA0_PLL_1P8
VDD_PCIE_IOB_1P8
VDD_PCIE_LDO_1P8
VDD_USB_HSIC0_1P8
VDD_HDMI_RX0_1P8
VDD_HDMI_TX0_1P8
8
--- 2 These 19 balls are tied to the
1.8 V SMPS supply through dual
120 Ω ferrite beads and filtered as
shown (see the i.MX8QM LPDDR4
MEK schematic for illustration). Place
the eight 2.2 µF caps under the
BGA package.
VDD_HDMI_TX0_1P0
VDD_HDMI_TX0_ LDO_1P0_CAP
2 --- --- Balls AW15 and AV16 of
the processor.
VDD_HDMI_RX0_LDOn_
1P0_CAP
4 --- --- Balls AU19 and AU21 of processor (2 x
2.2 µF per ball).
VDD_PCIE_LDO_1P0_CAP
VDD_PCIEn_1P0
VDD_PCIE_SATA0_1P0
2 --- --- Balls N29, M26, N25, and N24,
respectively to the processor.
VDD_USB3_SS3_LDO_
1P0_CAP VDD_USB_OTGn_1P0
3 --- --- Balls M30, M32, and N31, respectively
to the processor. Place two caps under
the BGA package.
VDD_SNVS_4P2 --- --- --- --- Ball AT38, use 0.22 µF.
VDD_SNVS_LDO_1P8_CAP --- 1 --- --- Ball AW39.
VDD_USB_HSIC0_1P2 1 --- --- Ball V26.
VDD_SIM0_1P8_3P3 1 --- --- --- Ball AK42.
VDD_USDHC1_1P8_3P3_n 1 --- --- --- Balls M36 and N37.
VDD_USDHC2_1P8_3P3_1 1 --- --- --- Ball M38.
VDD_ENET0_1P8_2P5_3P3_n 1 --- --- Balls M40 and N39.
VDD_ENET1_1P8_2P5_3P3 1 --- --- --- Ball T38.
Table continues on the next page...
NXP Semiconductors
i.MX8 QM and QXP design checklist
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 12 / 89
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