NXP Semiconductors PN544 C2 - Page 157

NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 157 of 172
Address Name Comment Default
0x9EAA
PWR_STATUS Indicates PN544 power modes used:
0x00 -> PN544 stays in active bat mode (except when generating RF
field)
0x01 -> PN544 goes in standby when possible otherwise stays in active
bat mode
0x02 -> RFU.
0x03 -> RFU.
0x00
0x9C0C
Host_TIC_MSB_RX
0x00
0x9C0D
Host_TIC_LSB_RX
T
IC
, inter-character timeout in Reception (in 3µs step)
(When Host is writing to PN544)
(0x0000 means T
IC
mechanism disabled, 0x0096 = 0,45ms)
0x96
0x9C12
Host_TIC_MSB_TX
0x20
0x9C13
Host_TIC_LSB_TX
T
IC
, inter-character timeout in Transmission (in 3µs step)
(When Host is reading from PN544)
(0x0000 means T
IC
mechanism disabled, 0x203A = 25ms)
0x3A
0x9C27
AckHostTimeout_MSB
0x00
0x9C28
AckHostTimeout_LSB
PN544 Ack Timeout on Host link.
(in 1ms step)
(0x0005 = 5ms)
0x05
0x9C31
GuardHostTimeoutMSB
0x00
0x9C32
GuardHostTimeoutLSB
Guard Host Timeout on Host link.
(in 1ms step)
(0x0000 means
resend mechanism disabled, 0x0032 = 50ms)
0x32
0x9C19
Host_RX_Retry
Maximum consecutive retries on host interface RX path before
deactivating (soft reset)
0x0A
0x9C1A
Host_TX_Retry
Maximum consecutive retries on host interface TX path before
deactivating (soft reset)
0x0A
0x9C1B
SWP_RX_Retry
Maximum consecutive retries on SWP RX path before deactivating (soft
reset)
0x0A
0x9C1C
SWP_TX_Retry
Maximum consecutive retries on SWP TX path before deactivating (soft
reset)
0x0A
0x9C18
SWP_Act_Retry
Maximum consecutive retries to activate SWP connection
0x03
0x9C41
IFSLEW
De/Activate IF0..3 pins slew rate control, default: activated
Set to 0x00 to deactivate it
0x0F
0x98A2
NFCT_TO
WT value to compute RWT (See [4])
(PN54
4 timeout will be half as specified)
0x09
0x98A3
NFCT_PPt
Define NAD handling on target side
Set to 0x30 to disable NAD usage
0x31