194
timers in the step are reset to their SVs. Counters, shift registers, and bits
used in KEEP(11) maintain status. Two simple steps are shown below.
SNXT(09) LR 2000
STEP(08) LR 2000
00000
Step controlled by LR 2000
SNXT(09) LR 2001
STEP(08) LR 2001
00001
Step controlled by LR 2001
SNXT(09) 2002
STEP(08)
00002
Starts step execution
Ends step execution
1st step
2nd step
Address Instruction Operands Address Instruction Operands
00000 LD 00000
00001 SNXT(09) LR 2000
00002 STEP(08) LR 2000
Step controlled by 20200.
00100 LD 00001
00101 SNXT(09) LR 2001
00102 STEP(08) LR 2001
Step controlled by 20201.
00200 LD 00002
00201 SNXT(09) LR 2002
00202 STEP(08) ---
Steps can be programmed in consecutively. Each step must start with
STEP(08) and generally ends with SNXT(09) (see example 3, below, for an
exception). When steps are programmed in series, three types of execution
are possible: sequential, branching, or parallel. The execution conditions for,
and the positioning of, SNXT(09) determine how the steps are executed. The
three examples given below demonstrate these three types of step execu-
tion.
Interlocks, jumps, SBN(92), and END(01) cannot be used within step pro-
grams.
Bits used as control bits must not be used anywhere else in the program un-
less they are being used to control the operation of the step (see example 3,
below). All control bits must be in the same word and must be consecutive.
If IR or LR bits are used for control bits, their status will be lost during any
power interruption. If it is necessary to maintain status to resume execution
at the same step, HR bits must be used.
Precautions
Step Instructions Section 5-21
To Next Page
Loading...
