Appendix BProgramming Instructions
293
IR SR HR TR AR LR TC DM #
00000 to 23515 23600 to 25507 HR 0000 to 9915 TR 0 to 7 AR 0000 to 2715 LR 0000 to 6315 TC 000 to 511 Read/Wr: DM 0000 to DM 0999
Rd only: DM 1000 to DM 1999
0000 to 9999
or 0000 to FFFF
These footnote tables show the actual ranges of all data areas. Bit numbers are provided (except for DM and TC areas); remove the rightmost two digits for word numbers.
Data Areas
Name
Mnemonic
Operand Data AreasFunctionSymbol
WORD SHIFT
(@)WSFT(16)
WSFT(16)
E
St
The data in the words from the starting
word (St) through to the ending word (E),
is shifted left in word units, writing all zeros
into the starting word. St must be less than
or equal to E, and St and E must be in the
same data area.
St/E:
IR
HR
AR
LR
DM
REVERSIBLE WORD
SHIFT
(@)RWS(17)
(CPU11-E)
RWS(17)
E
St
C
Creates and controls a reversible
non-synchronous word shift register be-
tween St and E. Exchanges the content of
a word containing zero with the content of
either the preceding or following word, de-
pending on the shift direction. Bits 13, 14,
and 15 of control word C determine the
mode of operation of the register accord-
ing to the following: The shift direction is
determined by bit 13 (OFF shifts the
non-zero data to higher addressed words;
ON to lower addressed words). Bit 14 is
the register enable bit (ON for shift en-
abled). Bit 15 is the reset bit (if bit 15 is ON,
the register will be set to zero between St
and E when the instruction is executed
with bit 14 also ON). St and E must be in
the same data area.
C:
IR
SR
HR
AR
LR
TC
DM
#
St/E:
IR
SR
HR
AR
LR
TC
DM
CYCLE TIME
(@)SCAN(18)
(CPU11-E)
SCAN(18)
Mi
–––
–––
Sets the minimum cycle time, Mi, in tenths
of milliseconds. The possible setting
range is from 0 to 999.0 ms. If the actual
cycle time is less than the time set using
SCAN(18), the CPU will wait until the des-
ignated time has elapsed before starting
the next cycle.
Mi:
IR
SR
HR
AR
LR
TC
DM
#
–––:
Not used.
MULTI-WORD
COMPARE
(@)MCMP(19)
(CPU11-E)
MCMP(19)
D
S
2
S
1
Compares the data within a block of 16
words of 4-digit hexadecimal data (S
1
to
S
1
+15) with that in another block of 16
words (S
2
to S
2
+15) on a word-by-word
basis. If the words are not in agreement,
the bit corresponding to unmatched words
turns ON in the result word, D. Bits corre-
sponding to words that are equal are
turned OFF.
S
1
/S
2
:
IR
SR
HR
AR
LR
TC
DM
D:
IR
SR
HR
AR
LR
TC
DM
COMPARE
(@)CMP(20)
CMP(20)
Cp1
Cp2
Compares the data in two 4-digit hexadeci-
mal words (Cp1 and Cp2) and outputs re-
sult to the GR, EQ, or LE Flags.
Cp1/Cp2:
IR
SR
HR
AR
LR
TC
DM
#
To Next Page
Loading...
