37
Instruction 1
0000
Instruction 2
0003
TR 0
0001
0004
0002
0001 0003
0000
0004
0002
0001
Instruction 1
Instruction 2
TR bits are only used when programming using mnemonic code and are not
necessary when inputting ladder diagrams directly, as is possible from a
GPC. The above limitations on the number of branching points requiring TR
bits and considerations on methods to reduce the number of programming
instructions still hold.
The problem of storing execution conditions at branching points can also be
handled by using the Interlock (IL(02)) and Interlock Clear (ILC(03)) instruc-
tions. When an Interlock instruction is placed at a branching point of an in-
struction line and the execution condition for the Interlock instruction is ON,
each branch line is established as an new instruction line, with the first condi-
tion on each branch line corresponding to a Load or Load NOT instruction. If
the execution condition for the Interlock instruction is OFF, all instructions on
the right side of the branch lines leading from the branching point receive an
OFF execution condition through the first Interlock Clear instruction. The ef-
fect that this has on particular instructions is described in
5–7 Interlock and
Interlock Clear – IL(02) and ILC(03).
Diagram B from the above example can also be corrected with an interlock.
As shown below, this requires one more instruction line for the Interlock Clear
instruction.
Instruction 1
0002
0000
Instruction 2
Diagram B: Corrected with an Interlock
0001
ILC(03)
IL(02)
If 0000 is ON in the above version of diagram B, the status of 0001 and that
of 0002 would determine the execution conditions for instructions 1 and 2,
respectively, on independent instruction lines. Because here 0000 is ON, this
would produce the same results as ANDing the status of each of these bits,
as would occur if the interlock was not used, i.e., the Interlock and Interlock
Note
Interlocks
The Ladder Diagram Section 4–3
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