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accordingly. The execution condition that was stored at the branching point is
then loaded back in (a Load instruction with TR 0 as the operand) and in-
struction 2 is executed accordingly.
The following example shows an application using two TR bits.
Instruction 1
0003
0000 0002
TR 1
0005
TR 0
0001
0004
Instruction 2
Instruction 3
Instruction 4
In this example, TR 0 and TR 1 are used to store the execution conditions at
the branching points. After executing instruction 1, the execution condition
stored in TR 1 is loaded for an AND with the status 0003. The execution con-
dition stored in TR 0 is loaded twice, the first time for an AND with the status
of 0004 and the second time for an AND with the inverse of the status of
0005.
TR bits can be used as many times as required as long as the same TR bit is
not used more than once in the same instruction block. Here, a new instruc-
tion block is begun each time execution returns to the bus bar. If more than
eight branching points requiring that the execution condition be saved are
necessary in a single instruction block, interlocks, which are described next,
must be used.
When drawing a ladder diagram, be careful not to use TR bits unless neces-
sary. Often the number of instructions required for a program can be reduced
and ease of understanding a program increased by redrawing a diagram that
would otherwise required TR bits. With both of the following pairs of dia-
grams, the versions on the top require fewer instructions and do not require
TR bits. The first example achieves this by merely reorganizing the parts of
the instruction block; the second, by separating the second Output instruction
and using another Load instruction to create the proper execution condition
for it.
Instruction 1
0000
Instruction 2
0001
TR 0
Instruction 2
0000
Instruction 1
0001
The Ladder Diagram Section 4–3
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