69
If the time it takes to count through some range is less than the scan time of
the CPU, the high-speed counter may count past between scans and thus
the output bit for this range may not be turned ON.
Counting Time
Lower Limit Upper Limit
The count signal must be at least 250 µs (2 kHz) wide and have a duty factor
of 1:1, as shown below.
250 µs 250 µs
Input
0000
In the hard reset mode, the reset signal must have an ON time of at least 250
µs.
250 µs max.
Input
0001
Description
The high-speed counter counts the signals input from an external device con-
nected to input 0000 and, when the high-speed counter instruction is ex-
ecuted, compares the current value with a set of ranges which have been
preset in DM words 32 through 63. If the current value is within any of the
preset ranges, the corresponding bit of a specified result word is turned ON.
The bit in the result word remains ON until the current value is no longer
within the specified range.
An internal buffer is incremented whenever bit 0000 goes from OFF to ON.
When the high-speed counter instruction is executed, the value in the count-
er buffer is transferred to counter 47 which serves as the count value storage
area.
When using the high-speed counter, the following bits are reserved and can-
not be used for any other purpose:
• Input 0000 (count input)
• Input 0001 (hard reset)
• IR bit 1807 (soft reset)
• TC 47 (present count value)
• DM 32 to 63 (upper and lower limits)
If a power failure occurs, the count value of the high speed counter immedi-
ately before the power failure is retained.
The high-speed counter is programmed differently depending on how it is to
be reset. Two resetting modes are possible: hard-reset and soft-reset. The
hard reset is made effective or ineffective with the DIP switch in the CPU.
General
Note
Timer and Counter Instructions Section 5–11
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