Panasonic AFPX-C30T - Page 323

High-speed counter when using pulse I/O cassette (AFPX-PLS)
Channel No.
Memory area being used
Performance specifications
Input
contact
Note1)
Control
flag
Elapsed
value
area
Target
value
area
Minimum
input pulse
width
Note2)
Maximum
counting speed
[Single phase]
Incremental,
Decremental
CH8
X100
(X102)
R9118
DT90332
DT90333
DT90334
DT90335
6.25
µs
(100
µs)
Single-phase 2
channels: 80 kHz
Single-phase 4
channels: 50 kHz
CH9
X101
(X102)
R9119
DT90336
DT90337
DT90338
DT90339
CHA
Note4)
X200
(X202)
R911A
DT90340
DT90341
DT90342
DT90343
CHB
Note4)
X201
(X202)
R911B
DT90344
DT90345
DT90346
DT90347
[2-phase]
2-phase input
One input
Direction
distinction
CH8
X100
X101
(X102)
R9118
DT90332
DT90333
DT90334
DT90335
16.7 µs
(100
µs)
2-phase 1
channel: 30 kHz
2-phase 2
channels: 25 kHz
CHA
Note4)
X200
X201
(X202)
R911A
DT90340
DT90341
DT90342
DT90343
Related instructions:
F0(MV) :High-speed counter control
F1(DMV) :Read/write of elapsed value of high-speed counter
F166(HC1S) :Target value match on
F167(CH1R) :Target value match off
Note1) The values in parentheses are for the reset input. The reset input X102 can be set to either CH8
or CH9. The reset input X202 can be set to either CHA or CHB.
Note2)
Reference: For information on minimum input pulse width,
<10.3.3 Minimum Input Pulse Width>.
Note3) When using the AFPX-PLS only
Note4) CHA/CHB can be used when 2 units of AFPX-PLS are installed.
Phone: 800.894.0412 - Fax: 888.723.4773 - Web: www.clrwtr.com - Email: info@clrwtr.com