Panasonic FPG-XY64D2P-A - Writing the High-Speed Counter Control Code

FPΣ User's Manual
7.3 High-Speed Counter Function
111
7.3.4.1 Writing the High-Speed Counter Control Code
The special data register where the high-speed counter and pulse output control code are
stored can be accessed with the system variable sys_wHscOrPulseControlCode. (The system
variable sys_wHscOrPulseControlCode corresponds to special data register DT90052.)
The control code settings for each channel can be monitored using the system variables
sys_wHscChannelxControlCode or sys_wPulseChannelxControlCode (where x=channel
number). The settings of this system variable remain unchanged until another setting
operation is executed.
Operations performed by the high-speed counter control code:
• Clearing high-speed counter instructions (bit 3)
• Enabling/disabling the reset input (hardware reset) of the high-speed counter (bit 2)
• Enabling/disabling counting operations (bit 1)
• Resetting the elapsed value (software reset) of the high-speed counter to 0 (bit 0)
Clearing high-speed counter instructions (bit 3)
To cancel execution of an instruction, set bit 3 of the data register storing the high-speed
counter control code (sys_wHscOrPulseControlCode) to TRUE. The high-speed counter
control flag then changes to FALSE. To reenable execution of the high-speed counter
instruction, reset bit 3 to FALSE.
Enabling/disabling the reset input (hardware reset) of the high-speed counter (bit 2)
0
01
2
X0
1
X2
t
3
4
X0 High-speed counter input
1
Elapsed value
2
Bit 2 of high-speed counter control code (enable/disable reset input)
3
Elapsed value is reset to 0
4
Reset not possible
When bit 2 of the control code is set to TRUE, a hardware reset using the reset input specified
in the system registers is not possible. Counting will continue even if the reset input has
turned to TRUE. The hardware reset is disabled until bit 2 is reset to 0.