Pioneer PDP-5000EX - Page 179

PDP-5000EX
179
5678
56
7
8
C
D
F
A
B
E
THC63LVD104S (FHD DIGITAL ASSY: IC3001, IC3002)
• LVDS Receiver IC
Pin Arrangement (Top view)
Block Diagram
Serial to Parallel
RA-
RA+
RA6-RA0
7
49RA-
50RA+
51RB-
52RB+
53LVCC
54RC-
55RC+
56RCLK-
57RCLK+
58LGND
59RD-
60RD+
61RE-
62RE+
63PGND
64PVCC
RB632
CLKOUT31
GND30
RC029
RC128
RC227
RC326
RC425
RC524
VCC23
RC622
RD021
RD120
RD219
RD318
RD417
VCC48 RA047 RA146 RA245 GND44 RA343 RA442 RA541 RA640 RB039 RB138 VCC37 RB236 RB335 RB434 RB533
1GND 2DK 3PD 4OE 5R/F 6RE6 7RE5 8RE4 9VCC 10RE3 11RE2 12RE1 13RE0 14RD6 15RD5 16GND
50
49
40-43,
45-47
RB-
RB+
RB6-RB0
52
51
32-36,
38,39
RC-
RC+
RC6-RC0
55
54
22,
24-29
RD-
RD+
RD6-RD0
60
59
14,15,
17-21
RE-
RE+
RE6-RE0
62
61
6-8,
10-13
RCLK-
RCLK+
(8 to 112 MHz)
CLKOUT
CMOS/TTL INPUT
CMOS/TTL OUTPUT
LVDS INPUT
PLL
57
31
R/F
5
DK
2
PD
3
OE
4
56
7
7
7
7