Operational Specifications 10
Copyright © profichip GmbH, 2012
AB10..0
DB7..0
XWR
valid
data valid
XCS
XREADY
(normal)
XREADY
(early)
22
27
26
25
30
23
28
16
29
19
20
21
Figure 10-12: Asynchronous Intel Mode, WRITE (XRD = 1)
address-setuptime to XRD / XWR
XCS setuptime to XRD / XWR
XRD to XREADY (Normal-Ready)
XRD to XREADY (Early-Ready)
address holdtime after XRD / XWR
XCS holdtime after XRD / XWR
XREADY holdtime after XRD / XWR
Figure 10-13: Timing, Asynchronous Intel Mode