Copyright © profichip GmbH, 2012
10.6.4 Timing in the Synchronous Motorola Mode
If the CPU is clocked by the VPC3+S, the output clock pulse (CLKOUT 2/4)
must be 4 times larger than the E_Clock. That is, a clock pulse signal must
be present at the CLK input that is at least 10 times larger than the desired
system clock pulse (E_Clock). The Divider-Pin must be connected to ‘0’
(divider 4). This results in an E_Clock of 3 MHz.
The request for a read access to the VPC3+S is derived from the rising
edge of the E_Clock (in addition: XCS = 0, R_W = 1). The request for a
write access is derived from the falling edge of the E_Clock (in addition:
XCS = 0, R_W = 0).
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