Copyright © profichip GmbH, 2012
10.6.3 Timing in the Asynchronous Intel Mode
In the asynchronous Intel mode, the VPC3+S acts like a memory with ready
logic. The access time depends on the type of access. The request for an
access to the VPC3+S is generated from the falling edge of the read signal
(XRD) or the rising edge of the write signal (XWR).
The VPC3+S generates the Ready signal synchronously to the system
clock. The Ready signal gets inactive when the read or the write signal is
deactivated. The data bus is switched to Tristate with XRD = '1'.
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