Profichip VPC3+S - Timing in SPI Interface Mode

Operational Specifications 10
VPC3+S User Manual
Revision 1.04
123
Copyright © profichip GmbH, 2012
10.6.6 Timing in SPI Interface Mode
SCK
(CPOL=0)
MISO
MOSI
t
HIGH.SCK
t
LOW.SCK
t
S.SI
t
S.XSS
SCK
(CPOL=1)
XSS
VALID OUT
VALID IN
t
H.SI
t
V.SO
t
H.SO
t
DIS.SO
HIGH IMPEDANCE
HIGH IMP.
t
HIGH.XSS
Figure 10-20: Timing Diagram SPI Interface Mode (CPHA='0')
SCK
(CPOL=0)
MISO
MOSI
t
HIGH.SCK
t
LOW.SCK
t
S.SI
t
S.XSS
SCK
(CPOL=1)
XSS
VALID OUT
VALID IN
t
H.SI
t
V.SO
t
H.SO
t
DIS.SO
HIGH IMPEDANCE
HIGH IMP.
t
HIGH.XSS
Figure 10-21: Timing Diagram SPI Interface Mode (CPHA='1')