Profichip VPC3+S - Application with 80 C32 (2 K Byte RAM Mode)

Hardware Interface 8
VPC3+S User Manual
Revision 1.04
105
Copyright © profichip GmbH, 2012
8.1.6 Application with 80C32 (2K Byte RAM Mode)
CLK
RESET
XCS
MODE
ALE
XWR
XRD
XTEST0
XTEST1
DIVIDER
48 MHz
1K
3K3
3K3
3K3
GND
VDD
µC
µC
µC
AB(15..8)
connect to
VDD or GND
XWR
XRD
5
8
36
1
23
24
2
4
34
35
3
44
43
41
40
37
42
32
31
29
25
10
CLK2
XDATAEX
XREADY
X/INT
XCTS
RXD
RTS
TXD
VPC3+
µC
1K
RS485
RS485
RS485
7
13
14
9
33
30
27
26
11
12
15
16
19
20
21
22
µC
DB(7..0)
GND
VDD
VDD
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
LED for Data_Exchange
XINT/MOT
µC
µC
3K3
VDD
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
1K
1K
1K
GND
1
Figure 8-23: 80C32 Application in 2K Byte mode
The internal chipselect is activated when the address inputs AB[10..3] of
the VPC3+S are set to '0'.
In the example above the start address of the VPC3+S is set to 1000H.
CS
decoder
4.0 KB
RAM
address
latch
8
8
5
3 11
1
ALE
AD[7..0]
AB[10..8]
all bits
zero
AB[15..11]
internal chip
select
internal address
ALE
DB[7..0]
AB[2..0]
Processor VPC3+ B
AB[7..3]
AB[10..8]
8
3
Figure 8-24: Internal Chipselect Generation in Synchronous Intel Mode, 2K Byte RAM