Profichip VPC3+S - Pin Assignment (Overview)

Pin Description 3
VPC3+S User Manual
Revision 1.04
11
Copyright © profichip GmbH, 2012
3.2 Pin Assignment (Overview)
Ball
BGA
Pin
QFP
Signal Name
In/Out
Description
Source / Destination
A1
48
AB8
I(S)
Address Bus 8
CPU
SPI_SCK / I2C_SCK
SPI: Serial Clock / I2C: Serial Clock
A2
47
XREADY / XDTACK
I(S)/O
READY / DTACK for external CPU
CPU
SPI_MISO / I2C_SDA
SPI: Master-In-Slave-Out / I2C: Serial Data
A3
7
GND
A4
6
VCC
A5
38
AB3
I
Address Bus 3
CPU
I2C_SA3
I2C: Slave Address 3
Configuration Pin
A6
37
AB2
I
Address Bus 2
CPU
I2C_SA2
I2C: Slave Address 2
Configuration Pin
B1
1
AB7
I(S)
Address Bus 7
CPU
SPI_MOSI
SPI: Master-Out-Slave-In
Configuration Pin
B2
46
AB5
I
Address Bus 5
CPU
I2C_SA5
I2C: Slave Address 5
Configuration Pin
B3
44
AB9
I
Address Bus 9
CPU
SPI_CPHA
SPI: Clock Phase
Configuration Pin
B4
41
AB4
I
Address Bus 4
CPU
I2C_SA4
I2C: Slave Address 4
Configuration Pin
B5
39
AB1
I
Address Bus 1
CPU
I2C_SA1
I2C: Slave Address 1
Configuration Pin
B6
36
AB0
I
Address Bus 0
CPU
I2C_SA0
I2C: Slave Address 0
Configuration Pin
C1
3
XCS
I
Chip-Select
CPU
SPI_XSS
SPI: Slave-Select
C2
2
AB10
I
Address Bus 10
CPU
SPI_CPOL
SPI: Clock Polarity
Configuration Pin
C3
45
AB6
I
Address Bus 6
CPU
I2C_SA6
I2C: Slave Address 6
Configuration Pin
C4
40
SYNC
O
Synchronization Pulse
CPU / Motion Control
C5
35
ALE /AS / AB11
I
Address Latch Enable / Address Strobe /
Address Bus 11
CPU
C6
34
XRD / R_W
I
Read / Read-Write
CPU
D1
18
VCC
D2
5
XTEST0
I
Test Pin 0 (to be connected to VCC)
Test Pin
D3
4
DIVIDER
I
Divider setting for CLKOUT: ‘0’: 12 MHz
‘1’: 24 MHz
Configuration Pin
D4
33
MODE
I
‘0’: Asynchronous Mode (Parallel Interface Mode)
‘1’: Synchronous Mode (Parallel Interface Mode)
‘0’: SPI (Serial Interface Mode)
‘1’: I2C (Serial Interface Mode)
Configuration Pin