Copyright © profichip GmbH, 2012
7.3.2.1 IsoM-PLL
The PLL shall handle following issues:
- The jitter of the SYNCH telegrams has to be smoothed by the PLL.
If the jitter exceeds a certain limit, the PLL will recognize a loss of
the synchronization.
- SYNCH telegrams lost due to bus disturbances have to be
compensated.
- Phase shifts due to line delay between the different DP-slaves may
be compensated.
- Generation of a SYNC clock in every slave cycle. The slave
application cycle time must be an integer part of DP cycle time.
PLL
Reset
Status
Parameter
Global_Control clock
(T
DP
)
Jitter <= 1 us
SYNC clock
(T
DP
/n)
Jitter <= 100 ns
t
DP-Cycle (T
DP
)
tolerance window
occurence of Global_Control
error
(delayed)
error
(missing)
ok
ok
GC_Clock_Hit
T
SYNC
Sync_PW_Reg
SYNC
GC_Clock_Detect
behaviour in case of: Enable_In_Clock=1, Enable_Out_Clock=1, Enable_GC_Clock=1
Number_of_SYNC=3, T
PLL_I
=3, T
PLL_O
=2
SYNC
GC_Clock_Detect
Out_Clock_Detect
In_Clock_Detect
Figure 7-20: SYNC clock and status signals of PLL
To enable the IsoM-PLL in the VPC3+S, bit PLL_Supported in Mode
Register 3 must be set and the IsoM must be parameterized. A
Structured_Prm_Data block for IsoM in the parameter telegram contains
the configuration values for the PLL.
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