Profichip VPC3+S - Page 75

PROFIBUS DP Extensions 7
VPC3+S User Manual
Revision 1.04
75
Copyright © profichip GmbH, 2012
The PLL can be used in Isochronous Mode only (not in Simple Sync
Mode). The user has to take care that the value of SYNC_PW_Reg
matches the SYNC cycle time, which could be smaller than the DP
cycle time now.
If E_limit is reached, a SYNC clock is generated, too.
Direction
Parameter
Description
IN
Global_Control clock
indicates arriving SYNCH telegram
PLL start
start and stop of PLL
SYNC mode
SYNC clock synchronized to Global_Control clock
SYNC enable
enable SYNC clock after successful synchronization
specific clock enable
enable only clock0, input or output clock
SYNC cycle time (T
SYNC
)
period of SYNC clock cycle; shall be an integer part
of DP cycle time
ratio of DP cycle to
SYNC cycle (n)
number of SYNC clock cycles per T
DP
E_limit
number of acceptable synchronization errors
input time (T
PLL_I
)
point in time for actual value acquisition
output time (T
PLL_O
)
point in time for setpoint transfer
PLL window (T
PLL_W
)
half the width of the tolerance window
First_Window
start value of PLL window
PLL delay time (T
PLL_D
)
delay of the generated SYNC clock, to compensate
phase shifts between slaves due to the runtimes of
SYNCH telegram
OUT
SYNC clock
output clock of the PLL
SYNCH error
synchronization errors detected, resynchronization
necessary
PLL synchronized
PLL is synchronized with the DP-Masters SYNCH
hit display
SYNCH telegram arrived within tolerance window
clock0 display
SYNC clock coincides with the (expected)
Global_Control clock
input clock display
SYNC clock designated for actual value acquisition
output clock display
SYNC clock designated for setpoint transfer
Figure 7-21: Inputs and outputs of the PLL