Profichip VPC3+S - Interrupt Request Register

ASIC Interface 5
VPC3+S User Manual
Revision 1.04
35
Copyright © profichip GmbH, 2012
The polarity of the interrupt output is parameterized via the Int_Pol bit in
Mode Register 0. After hardware reset, the output is low-active.
5.3.1 Interrupt Request Register
Address
Bit Position
Designation
7
6
5
4
3
2
1
0
00H
(Intel)
DXB_Out
New_Ext_ Prm_Data
DXB_Link_ Error
User_Timer_ Clock
WD_DP_ CONTROL_Timeout
Baud_Rate_ Detect
Go/Leave_ DATA-EXCH
MAC_Reset / Clock_Sync
Int-Req-Reg
7 .. 0
See below
for coding
Address
Bit Position
Designation
15
14
13
12
11
10
9
8
01H
(Intel)
FDL_Ind
Poll_End_Ind
DX_Out
Diag_Buffer_ Changed
New_Prm_ Data
New_Cfg_ Data
New_SSA_ Data
New_GC Command
Int-Req-Reg
15 .. 8
See below
for coding